[网络领域顶会追踪系列#10][NSDI'22]Tiara：一个针对有状态四层负载均衡的可扩展高效硬件加速架构

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Tiara: A Scalable and Efficient Hardware Acceleration Architecture for Stateful Layer-4 Load Balancing

背景

有状态的四层负载均衡器（Load Balancer, LB）被部署在数据中心边界，以分发互联网流量到后端的真实服务器（real server）。

挑战

为了驾驭Tbps级别的流量，传统的软件LB使用很多昂贵的服务器扩大规模。最近交换机加速的LB高效的扩展，但是没能将大量的并发流卸载至片上SRAM中。

工作

提出了Tiara，一个有状态四层LB的硬件架构，旨在不对流量模式做任何假设的前提下，支持高速流量（>1Tbps）和高并发流（>10M）。

Tiara的三层架构充分利用了有状态LB的异构硬件，包括快路径的可编程交换机和FPGA，以及慢路径的X86服务器。

Tiara的核心思想是划分LB的快路径为内存密集型任务（真实服务器选择）和吞吐密集型任务（数据包封装/解封装），并且分别映射它们到最合适的硬件（即映射真实服务器选择到用有大带宽内存的FPGA，映射数据包封装/解封装到高吞吐的可编程交换机）。

实验

实现了全功能的Tiara原型，实验表明在高开销、能源和空间效率的情况下，Tiara可以实现非常高的性能（1.6Tbps的吞吐、80M并发流、1.8M每秒的新连接和在一个装有8个FPGA的服务器上的快路径上小于4us的时延）

原文摘要

Stateful layer-4 load balancers (LB) are deployed at datacenter boundaries to distribute Internet traffic to backend real servers. To steer terabits per second traffic, traditional software LBs scale out with many expensive servers. Recent switch-accelerated LBs scale up efficiently, but fail to offload a massive number of concurrent flows into limited on-chip SRAMs.

This paper presents Tiara, a hardware architecture for stateful layer-4 LBs that aims to support a high traffic rate (> 1 Tbps), a large number of concurrent flows (> 10M), and many new connections per second (> 1M), without any assumption on traffic patterns. The three-tier architecture of Tiara makes the best use of heterogeneous hardware for stateful LBs, including a programmable switch and FPGAs for the fast path and x86 servers for the slow path. The core idea of Tiara is to divide the LB fast path into a memory-intensive task (real server selection) and a throughput-intensive task (packet encap/decap), and map them into the most suitable hardware, respectively (i.e., map real server selection into FPGA with large high-bandwidth memory (HBM) and packet encap/decap into a high-throughput programmable switch). We have implemented a fully functional Tiara prototype, and experiments show that Tiara can achieve extremely high performance (1.6 Tbps throughput, 80M concurrent flows, 1.8M new connections per second, and less than 4 us latency in the fast path) in a holistic server equipped with 8 FPGA cards, with high cost, energy, and space efficiency.